1. Field of the Invention
The present invention relates to a semiconductor memory device and to a circuit technology through which a low-voltage operation is implemented.
2. Background Art
Conventional art semiconductor memory devices include, for example, a semiconductor memory device disclosed in Patent Document 1, the configuration of a contact-type mask ROM is disclosed.
FIG. 12 is a circuit diagram showing the configuration of the contact-type mask ROM. With the contact-type mask ROM, whether the drains of memory cell transistors are connected to bit lines corresponds to the “1” and “0” states of storage data.
The conventional art semiconductor memory device shown in FIG. 12 includes a memory cell array 1, a column decoder 15, and a read circuit 16.
The memory cell array 1 includes memory cells M(i, j) (i=1 to m, and j=1 to n) each composed of a N-type MOS transistor and arranged in matrix form. As for the memory cells M (i, j), the gates of the memory cells M(i, j) whose positional symbols (i) represent the same numeric value, that is, the gates of the memory cells M(i, j) aligned in the row direction are together connected to common word line selection signal lines WLi (i=1 to m). Also, the sources of the memory cells M (i, j) are connected to a wiring having a ground potential.
When the drains of the memory cells M(i, j) (i=1 to m, and j=1 to n) are connected to bit lines BLj (j=1 to n), output data read from the memory cells M(i, j) (i=1 to m, and j=1 to n) to an output terminal MDATA becomes “1”, while in a floating state in which the connections are not made, output data read to the output terminal MDATA becomes “0”.
The column decoder 15 includes N-type MOS transistors QNCj (j=1 to n). The drains of the N-type MOS transistors QNCj (j=1 to n) are connected with one another, their sources are connected to the bit lines BLj (j=1 to n), and their gates are each connected to column selection signal lines CDj (j=1 to n).
The read circuit 16 includes P-type MOS transistors QPPS and QPL, a N-type MOS transistor QNRS, and an inverter INVA. With the P-type MOS transistor QPPS, its gate is connected to a precharge control signal line PCLK, its source is connected to a power supply potential line, and its drain is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15.
With the N-type MOS transistor QNRS, its gate is connected to a reset control signal line RSTS, its source is connected to a ground potential line, and its drain is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15.
With the inverter circuit INVA, its input end is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15, and its output end is connected to the output terminal MDATA.
With the P-type MOS transistor QPL, its gate is connected to the output end of the inverter INVA, its source is connected to the power supply potential line, and its drain is connected to the drains of the N-type MOS transistors QNCj (j=1 to n) constituting the column decoder 15.
The ON-state current of the P-type MOS transistor QPL is set so as to become smaller than those of the memory cells M(i, j) (i=1 to m, and j=1 to n) and to become equal to or larger than the total OFF leakage current of all the memory cells aligned on the single bit line.
The reading operation of data of, for example, the memory cell M(1, 1) of the semiconductor memory device having such a configuration will be described with reference to a FIG. 13 timing chart.
Among the column selection signal lines CDj (j=1 to n), the column selection signal line CD1 is brought high and the column selection signal lines CD2 to CDn are brought low. As a result, among the transistors constituting the column decoder 15, the transistor QNC1 is turned on and the other transistors QNC2 to QNCn are turned off.
Also, the reset control signal line RSTS is brought low and the transistor QNRS is turned off. Furthermore, all the word lines WL1 to WLm are brought low and all the memory cell transistors M(i, j) (i=1 to m, and j=1 to n) are turned off.
Then the precharge control signal line PCLK is held high for a fixed time period and the transistor QPPS is held on for a fixed time period, thereby the bit line BL1 is charged to the high level.
After the bit line BL1 has brought to high, the word line WL1 is shifted from the low level, which means a non-selected state, to the high level which means a selected state.
As a consequence, when the drain of the memory cell M(1, 1) is connected to the bit line BL1, electric charge supplied to the bit line BL1 is discharged by the memory cell M(1, 1), so that the bit line BL1 is brought low. In contrast to this, the drain of the memory cell M(1, 1) is not connected to the bit line BL1, the electric charge supplied to the bit line BL1 is not discharged by the memory cell M(1, 1), so that the bit line BL1 is held high.
Because of this, when the drain of the memory cell M(1, 1) is connected to the bit line BL1 to brought the bit line BL1 low, the low-level signal is inputted to the inverter INVA via the on-state transistor QNC1. As a result, the inverter INVA inputs a high-level signal to the gate of the transistor QPL to turn the transistor QPL off, thereby charging to the bit line BL1 is stopped and the high-level signal is outputted to the output terminal MDATA.
In contrast to this, when the drain of the memory cell M(1, 1) is not connected to the bit line BL1 to brought the bit line BL1 high, the high-level signal is inputted to the inverter INVA via the on-state transistor QNC1. As a consequence, the inverter INVA inputs a low-level signal to the gate of the transistor QPL to turn the transistor QPL on, thereby charging is effected to compensate for electric charge discharged from the bit line BL1 due to the OFF leakage currents of the memory cells M(i, 1) (i=1 to m) connected to the bit line BL1. As a result, the bit line BL1 is held high and a low-level signal is outputted to the output terminal MDATA.
Patent Document 1: Japanese Unexamined Patent Publication H06-176592. (page 2, paragraphs 0002 to 0006 and FIG. 2)
Problems brought about by the conventional art semiconductor memory device will be described below. With the configuration of the conventional art semiconductor memory device, the drains and sources of the transistors QNCj (j=1 to n) constituting the column decoder 15 are each connected to the read circuit 16 and the bit lines BLj (j=1 to n) without ground connections. Because of this, the threshold voltages at the transistors QNCj (j=1 to n) are increased by the substrate bias effect. The influence of the increased threshold voltages resulting from the substrate bias effect becomes large as the power supply voltage is decreased, so that the ON-state current of the transistors QNCj constituting the column decoder 15 is decreased greatly. Therefore, the supply of the electric charge to the bit lines BLj cannot be provided sufficiently by the transistor QPL provided to the read circuit 16 to compensate for the OFF leakage currents developed at the memory cells connected to the bit lines. As a consequence, the potentials at the drains of the transistors QNCj, which constitute the column decoder 15 connected to the read circuit 16, cannot be shifted to the low level, so that the potentials are held at the high level. Therefore, the function of the semiconductor memory device is impaired.
In recent years, as a need for operation effected with low power supply voltage has been increased rapidly with the advance of techniques for manufacturing smaller semiconductor devices, it has been particularly required that apparatus provided with semiconductor memory devices feature low power consumption to pursue their portability and so on. However, because of the suppression of power consumption increased by the OFF leakage current of transistors, it is difficult to lower the threshold voltage at the transistors; hence, this not only exists as a determinant of the range of the power supply voltage with which the semiconductor memory devices operate but brings about a big problem in the implementation of low-power semiconductor memory devices.
As a result, methods for lowering only the threshold voltage at some transistors during their manufacture and for reducing the substrate bias effect through the boost of the gate voltage at some transistors have been proposed. To lower the threshold voltage during their manufacture, however, there is a necessity to provide special manufacturing steps in addition to normal ones. In addition, to boost the gate voltage, there is a necessity to provide a booster circuit having a relatively large area, which brings about increases in not only the size of semiconductor memory devices but their production cost.